////////////////////////////////////////////////////////////////////////////////
//   ____  ____   
//  /   /\/   /  
// /___/  \  /   
// \   \   \/  
//  \   \        Copyright (c) 2003-2004 Xilinx, Inc.
//  /   /        All Right Reserved. 
// /---/   /\     
// \   \  /  \  
//  \___\/\___\
////////////////////////////////////////////////////////////////////////////////

#ifndef H_Xilinxcorelib_fifo_generator_v4_2_bhv_as_behavioral_H
#define H_Xilinxcorelib_fifo_generator_v4_2_bhv_as_behavioral_H
#ifdef __MINGW32__
#include "xsimMinGW.h"
#else
#include "xsim.h"
#endif


class Xilinxcorelib_fifo_generator_v4_2_bhv_as_behavioral: public HSim__s6 {
public:

  char *t883;
  char *t884;
  char *t885;
    HSim__s4 PE[40];
    HSim__s1 SE[25];

/* subprogram name actual_fifo_depth */
int Ff(const int C8, const int Ca, const int Cc);
/* subprogram name divroundup */
int Fu(const int Cp, const int Cr);
/* subprogram name int_2_std_logic */
char FQ(const int CM);
  int t886;
HSim__s4 C12;
HSim__s4 C18;
HSim__s4 C1e;
HSim__s4 C1n;
HSim__s4 C1x;
HSim__s4 C1F;
    HSimIncompleteType Incom_listtyp;
  HSimAccessType Listptr;
  HSimRecordType Listtyp;
/* subprogram name newlist */
void F4s(HSim__s7 *process,  HSimAccessVar &V4n,  HSimAccessVar &V4q);
/* subprogram name add */
void F4I(HSim__s7 *process,  HSimAccessVar &V4B,  HSimAccessVar &V4D, const char *C4G, const HSimConstraints *constrC4G);
/* subprogram name read */
void F5x(HSim__s7 *process,  HSimAccessVar &V5t,  char *V5v, const HSimConstraints *constrV5v);
/* subprogram name remove */
void F5J(HSim__s7 *process,  HSimAccessVar &V5F,  HSimAccessVar &V5H);
/* subprogram name sizeof */
void F6p(HSim__s7 *process,  HSimAccessVar &V6j,  int& V6m);
/* subprogram name count */
char *F71(HSimConstraints *reConstr, const int C6U, const int C6W, const int C6Y);
    HSim__s1 SA[41];
  char t887;
  char t888;
    Xilinxcorelib_fifo_generator_v4_2_bhv_as_behavioral(const char * name);
    ~Xilinxcorelib_fifo_generator_v4_2_bhv_as_behavioral();
    void constructObject();
    void constructPorts();
    void reset();
    void architectureInstantiate(HSimConfigDecl* cfg);
    virtual void vhdlArchImplement();
};



HSim__s6 *createXilinxcorelib_fifo_generator_v4_2_bhv_as_behavioral(const char *name);

#endif
