////////////////////////////////////////////////////////////////////////////////
//   ____  ____   
//  /   /\/   /  
// /___/  \  /   
// \   \   \/  
//  \   \        Copyright (c) 2003-2004 Xilinx, Inc.
//  /   /        All Right Reserved. 
// /---/   /\     
// \   \  /  \  
//  \___\/\___\
////////////////////////////////////////////////////////////////////////////////

#ifndef H_Work_sx2_interface_v2_H
#define H_Work_sx2_interface_v2_H
#ifdef __MINGW32__
#include "xsimMinGW.h"
#else
#include "xsim.h"
#endif


class Work_sx2_interface_v2: public HSim__s6 {
public:

  char *t0;
  char *t1;
    HSim__s4 PE[1];
    HSim__s1 SE[34];

HSim__s4 Ce;
  HSimEnumType Ep_arbiter_state_type;
  char *t2;
  char *t3;
  char *t4;
HSim__s4 C2r;
HSim__s4 C2u;
HSim__s4 C2x;
HSim__s4 C2A;
HSim__s4 C2D;
HSimConstraints *c5;
HSim__s4 C2N;
HSim__s4 C30;
  HSimArrayType Enum_arraybase;
  HSimArrayType Enum_array;
  HSimEnumType State_type;
    HSim__s1 SA[47];
  char t6;
    Work_sx2_interface_v2(const char * name);
    ~Work_sx2_interface_v2();
    void constructObject();
    void constructPorts();
    void reset();
    void architectureInstantiate(HSimConfigDecl* cfg);
    virtual void vhdlArchImplement();
};



HSim__s6 *createWork_sx2_interface_v2(const char *name);

#endif
