////////////////////////////////////////////////////////////////////////////////
//   ____  ____   
//  /   /\/   /  
// /___/  \  /   
// \   \   \/  
//  \   \        Copyright (c) 2003-2004 Xilinx, Inc.
//  /   /        All Right Reserved. 
// /---/   /\     
// \   \  /  \  
//  \___\/\___\
////////////////////////////////////////////////////////////////////////////////

#ifndef H_Xilinxcorelib_fifo_generator_v4_2_bhv_ss_behavioral_H
#define H_Xilinxcorelib_fifo_generator_v4_2_bhv_ss_behavioral_H
#ifdef __MINGW32__
#include "xsimMinGW.h"
#else
#include "xsim.h"
#endif


class Xilinxcorelib_fifo_generator_v4_2_bhv_ss_behavioral: public HSim__s6 {
public:

  char *t839;
  char *t840;
  char *t841;
  char *t842;
  char *t843;
  char *t844;
  char *t845;
  char *t846;
  char *t847;
  char *t848;
  char *t849;
    HSim__s4 PE[50];
    HSim__s1 SE[32];

/* subprogram name actual_fifo_depth */
int Fh(const int C8, const int Ca, const int Cc, const int Ce);
/* subprogram name int_2_std_logic */
char Fs(const int Cp);
  int t850;
HSim__s4 CE;
HSim__s4 CL;
    HSimIncompleteType Incom_listtyp;
  HSimAccessType Listptr;
  HSimRecordType Listtyp;
/* subprogram name newlist */
void F2x(HSim__s7 *process,  HSimAccessVar &V2t,  HSimAccessVar &V2v);
/* subprogram name add */
void F2N(HSim__s7 *process,  HSimAccessVar &V2G,  HSimAccessVar &V2I, const char *C2L, const HSimConstraints *constrC2L);
/* subprogram name read */
void F3C(HSim__s7 *process,  HSimAccessVar &V3y,  char *V3A, const HSimConstraints *constrV3A);
/* subprogram name remove */
void F3P(HSim__s7 *process,  HSimAccessVar &V3K,  HSimAccessVar &V3M);
/* subprogram name sizeof */
void F4u(HSim__s7 *process,  HSimAccessVar &V4q,  int& V4s);
/* subprogram name count */
char *F56(HSimConstraints *reConstr, const int C4Z, const int C51, const int C53);
    HSim__s1 SA[23];
  char t851;
  char t852;
    Xilinxcorelib_fifo_generator_v4_2_bhv_ss_behavioral(const char * name);
    ~Xilinxcorelib_fifo_generator_v4_2_bhv_ss_behavioral();
    void constructObject();
    void constructPorts();
    void reset();
    void architectureInstantiate(HSimConfigDecl* cfg);
    virtual void vhdlArchImplement();
};



HSim__s6 *createXilinxcorelib_fifo_generator_v4_2_bhv_ss_behavioral(const char *name);

#endif
