LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
entity version is
    port(
        rev_output: out std_logic_vector(31 downto 0)
    );
end entity version;--
architecture v0 of version is
begin
  rev_output<="00000000000000000000000000000110";
end architecture v0;
