The following files were generated for 'trigger_record_buf' in directory 
/home/matt/project/calice/master_controller/cores/coregen/:

trigger_record_buf_readme.txt:
   Text file indicating the files generated and how they are used.

trigger_record_buf.vho:
   VHO template file containing code that can be used as a model for
   instantiating a CORE Generator module in a VHDL design.

trigger_record_buf.vhd:
   VHDL wrapper file provided to support functional simulation. This
   file contains simulation model customization data that is passed to
   a parameterized simulation model for the core.

trigger_record_buf_xmdf.tcl:
   ISE Project Navigator interface file. ISE uses this file to determine
   how the files output by CORE Generator for the core can be integrated
   into your ISE project.

trigger_record_buf.ngc:
   Binary Xilinx implementation netlist file containing the information
   required to implement the module in a Xilinx (R) FPGA.

trigger_record_buf.xco:
   CORE Generator input file containing the parameters used to
   regenerate a core.

trigger_record_buf_flist.txt:
   Text file listing all of the output files produced when a customized
   core was generated in the CORE Generator.


Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.

