library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity trig_output is

  port(
    clk: in std_logic;
    trig_in: in std_logic;
    trig_out: out std_logic
    );

end entity trig_output;

architecture v0 of trig_output is

  signal int_reg0: std_logic;
  signal int_reg1: std_logic;

begin 

  reg_trig:process(clk)
  begin
    if(rising_edge(clk))then 
      int_reg0<=trig_in; 
      int_reg1<=int_reg0;
    end if;
  end process reg_trig;

  trig_out<=int_reg1;
  
end architecture v0;
