LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
entity build_time is
    port(
        build_utc_output: out std_logic_vector(31 downto 0)
    );
end entity build_time;--
architecture v0 of build_time is
begin
  build_utc_output<="01001010011001011100101101110101";
end architecture v0;
