////////////////////////////////////////////////////////////////////////////////
//   ____  ____   
//  /   /\/   /  
// /___/  \  /   
// \   \   \/  
//  \   \        Copyright (c) 2003-2004 Xilinx, Inc.
//  /   /        All Right Reserved. 
// /---/   /\     
// \   \  /  \  
//  \___\/\___\
////////////////////////////////////////////////////////////////////////////////

#ifndef H_Xilinxcorelib_iputils_conv_H
#define H_Xilinxcorelib_iputils_conv_H

#ifdef __MINGW32__
#include "xsimMinGW.h"
#else
#include "xsim.h"
#endif


#include "ieee/std_logic_1164/std_logic_1164.h"
#include "std/textio/textio.h"

class Xilinxcorelib_iputils_conv: public HSim__s6 {
public:
/* subprogram name rat */
char Gg(const char Ec);
/* subprogram name std_logic_vector_2_string */
char *Gp(HSimConstraints *reConstr, const char *Ek, const HSimConstraints *constrEk);
/* subprogram name std_logic_2_string */
char *Gv(HSimConstraints *reConstr, const char Es);
/* subprogram name std_logic_vector_2_int */
int GB(const char *Ey, const HSimConstraints *constrEy);
/* subprogram name two_comp */
char *GH(HSimConstraints *reConstr, const char *EE, const HSimConstraints *constrEE);
/* subprogram name int_2_std_logic_vector */
char *GR(HSimConstraints *reConstr, const int EL, const int EN);
/* subprogram name std_logic_vector_2_posint */
int GX(const char *EU, const HSimConstraints *constrEU);
/* subprogram name int_2_boolean */
char G13(const int E10);
/* subprogram name int_2_string */
char *G1b(HSimConstraints *reConstr, const int E16, const int E18);
/* subprogram name bint_2_sl */
char G1h(const int E1e);
/* subprogram name str_to_slv_0 */
char *G1s(HSimConstraints *reConstr, const char *E1m, const HSimConstraints *constrE1m, const int E1p);
/* subprogram name number_of_bits */
int G1y(const int E1v);
/* subprogram name number_of_digits */
int G1G(const int E1B, const int E1D);
/* subprogram name conv_int_to_new_radix */
char *G1R(HSimConstraints *reConstr, const int E1J, const int E1L, const int E1N);
/* subprogram name int_2_hex */
char *G1Z(HSimConstraints *reConstr, const int E1U, const int E1W);
/* subprogram name bin_2_hex_string */
char *G25(HSimConstraints *reConstr, const char *E22, const HSimConstraints *constrE22);
/* subprogram name hexstr_to_std_logic_vec */
char *G2d(HSimConstraints *reConstr, const char *E28, const HSimConstraints *constrE28, const int E2a);

public:
/* subprogram name div4roundup_v2 */
int Fdz(const int Cdw);

public:
  Xilinxcorelib_iputils_conv(const HSimString &name);
  ~Xilinxcorelib_iputils_conv();
};

extern Xilinxcorelib_iputils_conv *XilinxcorelibIputils_conv;

#endif
