The zip file contains the source directory, read_me.txt and no_generic_unisim.vhd file.

FED V1:	Must enable the XIL_VIRTEX2_PKG_USEALT environment variable ie set to 1.
			Must use BE_FPGA_FED_V1.ucf

FED V2: 	Must disable the XIL_VIRTEX2_PKG_USEALT environment variable ie set to 0 or delete.
			Must use BE_FPGA_FED_V2.ucf

The source path is: D:\CMS_FED\back_end_fpga\src

The no_generic_unisim.vhd must be placed in folder: 
D:\users\libraries\xilinx\unisim_no_generic\no_generic_unisim.vhd

Must place core generated edn files in the directory where ISE project is placed:
	For firmware version 0x12000239 onward, must put new *.edn files for the core generated FIFOs
	into the ISE project folder. (these FIFOs have 3-bit fifo write ports rather than 2-bits in
	the previous version)

Must sysnthesise the design using the TCL files provided for the 2000 device.

Time resolution for simulation must be set to ps.


